The James Webb Space Telescope is one of the most technically complex instruments humanity has ever built. It sits at the L2 Lagrange point, roughly 1.5 million kilometers from Earth, and peers into the universe in infrared light with a precision previously impossible. The onboard computer running all of this is a BAE Systems RAD750, a radiation-hardened processor based on the PowerPC 750 architecture. It has a maximum clock speed of 200 MHz. It is, for all practical purposes, a chip designed at the turn of the millennium.

That is not an accident or a cost-cutting measure. The RAD750 had flown on more than 150 spacecraft before TWST launched. It was proven, space-qualified, and trusted. NASA, as an institution, does not change what is working. The Curiosity and Perseverance Mars rovers both run the same chip. For missions that cost billions and cannot be repaired, conservatism is rational.

But conservatism has limits. Future mission requirements, covering autonomous planetary landing, real-time AI-driven science processing, and multi-node distributed sensor networks on the lunar surface, cannot be met by a 200 MHz single-core processor. The computational gap between what NASA is flying today and what it needs to fly tomorrow is not incremental. It is, by NASA’s own figures, a factor of at least 100.

That is the problem NASA set out to solve in 2022. The solution reached for was a 12-core RISC-V SoC built around processor IP from SiFive. The chip, now formally branded by Microchip Technology as the PIC64-HPSC, sits at the center of NASA’s High-Performance Spaceflight Computing (HPSC) program. It is also running behind its published schedule as of early 2026.